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» Analysis of communication delay bounds for network on chips
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INFOCOM
2010
IEEE
13 years 5 months ago
On Space-Time Capacity Limits in Mobile and Delay Tolerant Networks
We investigate the fundamental capacity limits of space-time journeys of information in mobile and Delay Tolerant Networks (DTNs), where information is either transmitted or carrie...
Philippe Jacquet, Bernard Mans, Georgios Rodolakis
INFOCOM
1993
IEEE
13 years 12 months ago
A Generalized Processor Sharing Approach to Flow Control in Integrated Services Networks: The Multiple Node Case
Worst-casebounds on delay and backlog are derived for leaky bucket constrained sessions in arbitrary topology networks of Generalized Processor Sharing (GPS) 10] servers. The inhe...
Abhay K. Parekh, Robert G. Gallager
SLIP
2006
ACM
14 years 1 months ago
Energy/area/delay trade-offs in the physical design of on-chip segmented bus architecture
— The increasing gap between design productivity and chip complexity and the emerging Systems-On-Chip (SOC) architectural template have led to the wide utilization of reusable ha...
Jin Guo, Antonis Papanikolaou, Pol Marchal, Franck...
INFOCOM
1996
IEEE
13 years 12 months ago
Latency-Rate Servers: A General Model for Analysis of Traffic Scheduling Algorithms
In this paper, we develop a general model, called Latency-Rate servers (LR servers), for the analysis of traffic scheduling algorithms in broadband packet networks. The behavior of...
Dimitrios Stiliadis, Anujan Varma
CN
2002
85views more  CN 2002»
13 years 7 months ago
Analysis of delay and delay jitter of voice traffic in the Internet
In the future, voice communication is expected to migrate from the public switched telephone network to the Internet. Because of the particular characteristics (low volume and bur...
Mansour J. Karam, Fouad A. Tobagi