Sciweavers

66 search results - page 10 / 14
» Analysis of path exclusion at the machine code level
Sort
View
RTAS
1998
IEEE
13 years 11 months ago
Bounding Loop Iterations for Timing Analysis
Static timing analyzers need to know the minimum and maximum number of iterations associated with each loop in a real-time program so accurate timing predictions can be obtained. ...
Christopher A. Healy, Mikael Sjödin, Viresh R...
ICDE
2010
IEEE
244views Database» more  ICDE 2010»
14 years 6 months ago
Propagating Updates Through XML Views Using Lineage Tracing
We address the problem of updating XML views over relational data by translating view updates expressed in the XQuery update facility to embedded SQL updates. Although our XML view...
Leonidas Fegaras
ISCAS
2005
IEEE
155views Hardware» more  ISCAS 2005»
14 years 9 days ago
Hyperblock formation: a power/energy perspective for high performance VLIW architectures
— Architectures based on Very Long Instruction Word (VLIW) processors are an optimal choice in the attempt to obtain high performance levels in mobile devices. The effectiveness ...
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi,...
ECLIPSE
2005
ACM
13 years 8 months ago
NaCIN: an Eclipse plug-in for program navigation-based concern inference
In this paper we describe NaCIN, an Eclipse plug-in that records a developer’s code navigation activity and produces sets of elements potentially implementing different concerns...
Imran Majid, Martin P. Robillard
ICCAD
2006
IEEE
169views Hardware» more  ICCAD 2006»
14 years 3 months ago
Microarchitecture parameter selection to optimize system performance under process variation
Abstract— Design variability due to within-die and die-todie process variations has the potential to significantly reduce the maximum operating frequency and the effective yield...
Xiaoyao Liang, David Brooks