29 search results - page 2 / 6 » Analyzing Cache Bandwidth on the Intel Core 2 Architecture |
ISCA
2005
IEEE
14 years 1 months ago
2005
IEEE
This paper examines the area, power, performance, and design issues for the on-chip interconnects on a chip multiprocessor, attempting to present a comprehensive view of a class o...
FPGA
2000
ACM
13 years 11 months ago
2000
ACM
A considerable portion of a chip is dedicated to a cache memory in a modern microprocessor chip. However, some applications may not actively need all the cache storage, especially...
ICCD
2000
IEEE
14 years 4 months ago
2000
IEEE
Secure socket layer SSL is the most popular protocol used in the Internet for facilitating secure communications through authentication, encryption, and decryption. Although the...
IWMM
2011
Springer
12 years 10 months ago
2011
Springer
Multiprocessors based on processors with multiple cores usually include a non-uniform memory architecture (NUMA); even current 2-processor systems with 8 cores exhibit non-uniform...
HPCA
2011
IEEE
12 years 11 months ago
2011
IEEE
Future CMPs will combine many simple cores with deep cache hierarchies. With more cores, cache resources per core are fewer, and must be shared carefully to avoid poor utilization...