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» Analyzing Loop Paths for Execution Time Estimation
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ASPDAC
2001
ACM
130views Hardware» more  ASPDAC 2001»
13 years 11 months ago
Area/delay estimation for digital signal processor cores
Hardware/software partitioning is one of the key processes in a hardware/software cosynthesis system for digital signal processor cores. In hardware/software partitioning, area and...
Yuichiro Miyaoka, Yoshiharu Kataoka, Nozomu Togawa...
JTRES
2010
ACM
13 years 7 months ago
WCET driven design space exploration of an object cache
In order to guarantee that real-time systems meet their timing specification, static execution time bounds need to be calculated. Not considering execution time predictability led...
Benedikt Huber, Wolfgang Puffitsch, Martin Schoebe...
IROS
2006
IEEE
83views Robotics» more  IROS 2006»
14 years 1 months ago
Using Orthogonal Surface Directions for Autonomous 3D-Exploration of Indoor Environments
— This paper proposes a new tracking algorithm within a 3D-SLAM framework that takes segmented range images as observations. The framework has two layers: the local layer tracks ...
Peter Kohlhepp, Georg Bretthauer, Marcus Walther, ...
MOBISYS
2004
ACM
14 years 7 months ago
NWSLite: A Light-Weight Prediction Utility for Mobile Devices
Computation off-loading, i.e., remote execution, has been shown to be effective for extending the computational power and battery life of resource-restricted devices, e.g., hand-h...
Selim Gurun, Chandra Krintz, Richard Wolski
DAC
2009
ACM
14 years 8 months ago
Online cache state dumping for processor debug
Post-silicon processor debugging is frequently carried out in a loop consisting of several iterations of the following two key steps: (i) processor execution for some duration, fo...
Anant Vishnoi, Preeti Ranjan Panda, M. Balakrishna...