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132
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CGO
2004
IEEE
15 years 6 months ago
Custom Data Layout for Memory Parallelism
In this paper, we describe a generalized approach to deriving a custom data layout in multiple memory banks for array-based computations, to facilitate high-bandwidth parallel mem...
Byoungro So, Mary W. Hall, Heidi E. Ziegler
145
Voted
ASPLOS
2004
ACM
15 years 8 months ago
Compiler orchestrated prefetching via speculation and predication
This paper introduces a compiler-orchestrated prefetching system as a unified framework geared toward ameliorating the gap between processing speeds and memory access latencies. ...
Rodric M. Rabbah, Hariharan Sandanagobalane, Mongk...
168
Voted
AAAIDEA
2005
IEEE
15 years 8 months ago
Design and Evaluation of Diffserv Functionalities in the MPLS Edge Router Architecture
—Differentiated Service (DiffServ) in combination with Multi-Protocol Label Switching (MPLS) is a promising technology in converting the best-effort Internet into a QoS-capable n...
Wei-Chu Lai, Kuo-Ching Wu, Ting-Chao Hou
135
Voted
RTAS
2005
IEEE
15 years 8 months ago
Bounding Worst-Case Data Cache Behavior by Analytically Deriving Cache Reference Patterns
While caches have become invaluable for higher-end architectures due to their ability to hide, in part, the gap between processor speed and memory access times, caches (and partic...
Harini Ramaprasad, Frank Mueller
141
Voted
PARCO
2003
15 years 4 months ago
Cache Memory Behavior of Advanced PDE Solvers
Three different partial differential equation (PDE) solver kernels are analyzed in respect to cache memory performance on a simulated shared memory computer. The kernels implement...
Dan Wallin, Henrik Johansson, Sverker Holmgren