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ICCAD
2001
IEEE
91views Hardware» more  ICCAD 2001»
14 years 4 months ago
A System for Synthesizing Optimized FPGA Hardware from MATLAB
Efficient high level design tools that can map behavioral descriptions to FPGA architectures are one of the key requirements to fully leverage FPGA for high throughput computatio...
Malay Haldar, Anshuman Nayak, Alok N. Choudhary, P...
ACSAC
2006
IEEE
14 years 2 months ago
Addressing SMTP-Based Mass-Mailing Activity within Enterprise Networks
Malicious mass-mailing activity on the Internet is a serious and continuing threat that includes mass-mailing worms, spam, and phishing. A mechanism commonly used to deliver such ...
David Whyte, Paul C. van Oorschot, Evangelos Krana...
IPPS
2006
IEEE
14 years 1 months ago
Parallelization of module network structure learning and performance tuning on SMP
As an extension of Bayesian network, module network is an appropriate model for inferring causal network of a mass of variables from insufficient evidences. However learning such ...
Hongshan Jiang, Chunrong Lai, Wenguang Chen, Yuron...
SC
2005
ACM
14 years 1 months ago
Scheduling speculative tasks in a compute farm
Users often behave speculatively, submitting work that initially they do not know is needed. Farm computing often consists of single node speculative tasks issued by, e.g., bioinf...
David Petrou, Garth A. Gibson, Gregory R. Ganger
ISVLSI
2003
IEEE
147views VLSI» more  ISVLSI 2003»
14 years 1 months ago
Automated Dynamic Memory Data Type Implementation Exploration and Optimization
The behavior of many algorithms is heavily determined by the input data. Furthermore, this often means that multiple and completely different execution paths can be followed, also...
Marc Leeman, Chantal Ykman-Couvreur, David Atienza...