422 search results - page 80 / 85 » Application mapping for chip multiprocessors |
ICES
2005
Springer
14 years 3 months ago
2005
Springer
This paper describes circuit evolutionary experiments at extreme low temperatures, including the test of all system components at this extreme environment (EE). In addition to hard...
ISNN
2005
Springer
14 years 3 months ago
2005
Springer
Abstract. Artificial Neural Networks (ANNs) and image processing requires massively parallel computation of simple operator accompanied by heavy memory access. Thus, this type of ...
IPPS
2002
IEEE
14 years 2 months ago
2002
IEEE
In this paper we present new approaches to high performance protein database scanning on two novel massively parallel architectures to gain supercomputer power at low cost. The ...
DNA
2001
Springer
14 years 2 months ago
2001
Springer
In the universal DNA chip method, target RNAs are mapped onto a set of DNA tags. Parallel hybridization of these tags with an indexed, complementary antitag array then provides an ...
IPPS
1999
IEEE
14 years 2 months ago
1999
IEEE
An e cient implementations of the main building block in the RSA cryptographic scheme is achieved by mapping a bit-level systolic array for modular exponentiation onto Xilinx FPGAs...