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» Application of Reduce Order Modeling to Time Parallelization
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IPPS
2007
IEEE
14 years 4 months ago
Power-Aware Speedup
Power-aware processors operate in various power modes to reduce energy consumption with a corresponding decrease in peak processor throughput. Recent work has shown power-aware cl...
Rong Ge, Kirk W. Cameron
ISCA
1998
IEEE
128views Hardware» more  ISCA 1998»
14 years 2 months ago
Analytic Evaluation of Shared-memory Systems with ILP Processors
This paper develops and validates an analytical model for evaluating various types of architectural alternatives for shared-memory systems with processors that aggressively exploi...
Daniel J. Sorin, Vijay S. Pai, Sarita V. Adve, Mar...
SOFTWARE
2011
13 years 5 months ago
Object-Oriented Parallelisation of Java Desktop Programs
Developing parallel applications is notoriously difficult, but is even more complex for desktop applications. The added difficulties are primarily because of their interactive nat...
Nasser Giacaman, Oliver Sinnen
CORR
2008
Springer
66views Education» more  CORR 2008»
13 years 10 months ago
A Novel Approach to Formulae Production and Overconfidence Measurement to Reduce Risk in Spreadsheet Modelling
Research on formulae production in spreadsheets has established the practice as high risk yet unrecognised as such by industry. There are numerous software applications that are d...
Simon R. Thorne, David Ball, Zoe Lawson
WSC
2004
13 years 11 months ago
Approximate Time-Parallel Cache Simulation
In time-parallel simulation, the simulation time axis is decomposed into a number of slices which are assigned to parallel processes for concurrent simulation. Although a promisin...
Tobias Kiesling