Sciweavers

3171 search results - page 70 / 635
» Application of Reduce Order Modeling to Time Parallelization
Sort
View
111
Voted
ISCAS
2006
IEEE
82views Hardware» more  ISCAS 2006»
15 years 8 months ago
Timing optimization of interconnect by simultaneous net-ordering, wire sizing and spacing
– This paper addresses the problem of ordering and sizing parallel wires in a single metal layer within an interconnect channel of a given width, such that crosscapacitances are ...
Konstantin Moiseev, Shmuel Wimer, Avinoam Kolodny
141
Voted
HPCA
2011
IEEE
14 years 6 months ago
Dynamic parallelization of JavaScript applications using an ultra-lightweight speculation mechanism
As the web becomes the platform of choice for execution of more complex applications, a growing portion of computation is handed off by developers to the client side to reduce net...
Mojtaba Mehrara, Po-Chun Hsu, Mehrzad Samadi, Scot...
134
Voted
WEA
2005
Springer
176views Algorithms» more  WEA 2005»
15 years 8 months ago
High-Performance Algorithm Engineering for Large-Scale Graph Problems and Computational Biology
Abstract. Many large-scale optimization problems rely on graph theoretic solutions; yet high-performance computing has traditionally focused on regular applications with high degre...
David A. Bader
156
Voted
DFT
2006
IEEE
203views VLSI» more  DFT 2006»
15 years 8 months ago
Self Testing SoC with Reduced Memory Requirements and Minimized Hardware Overhead
This paper describes a methodology of creating a built-in diagnostic system of a System on Chip and experimental results of the system application on the AT94K FPSLIC with cores d...
Ondrej Novák, Zdenek Plíva, Jiri Jen...
131
Voted
CCE
2005
15 years 2 months ago
Use of parallel computers in rational design of redundant sensor networks
A general method to design optimal redundant sensor network even in the case of one sensor failure and able to estimate process key parameters within a required accuracy is propos...
Carine Gerkens, Georges Heyen