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ASPLOS
2008
ACM
13 years 9 months ago
SoftSig: software-exposed hardware signatures for code analysis and optimization
Many code analysis techniques for optimization, debugging, or parallelization need to perform runtime disambiguation of sets of addresses. Such operations can be supported efficie...
James Tuck, Wonsun Ahn, Luis Ceze, Josep Torrellas
ISSS
1999
IEEE
168views Hardware» more  ISSS 1999»
13 years 11 months ago
Automatic Architectural Synthesis of VLIW and EPIC Processors
This paper describes a mechanism for automatic design and synthesis of very long instruction word (VLIW), and its generalization, explicitly parallel instruction computing rocesso...
Shail Aditya, B. Ramakrishna Rau, Vinod Kathail
IPPS
1998
IEEE
13 years 11 months ago
Partitioned Schedules for Clustered VLIW Architectures
This paper presents results on a new approach to partitioning a modulo-scheduled loop for distributed execution on parallel clusters of functional units organized as a VLIW machin...
Marcio Merino Fernandes, Josep Llosa, Nigel P. Top...
NPC
2005
Springer
14 years 1 months ago
Adaptive Query-Caching in Peer-to-Peer Systems
Peer-to-Peer (P2P) architectures are very prevalent in today’s Internet. Lots of P2P file sharing systems using Gnutella protocol emerge out and draw attractions of millions of p...
Zuoning Yin, Hai Jin, Chao Zhang, Quan Yuan, Chuch...
SIGMETRICS
2006
ACM
116views Hardware» more  SIGMETRICS 2006»
14 years 1 months ago
Applying architectural vulnerability Analysis to hard faults in the microprocessor
In this paper, we present a new metric, Hard-Fault Architectural Vulnerability Factor (H-AVF), to allow designers to more effectively compare alternate hard-fault tolerance scheme...
Fred A. Bower, Derek Hower, Mahmut Yilmaz, Daniel ...