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DFT
1999
IEEE
131views VLSI» more  DFT 1999»
14 years 14 days ago
Optimal Vector Selection for Low Power BIST
In the last decade, researchers have devoted increasing efforts to reduce the average power consumption in VLSI systems during normal operation mode, while power consumption durin...
Fulvio Corno, Matteo Sonza Reorda, Maurizio Rebaud...
INFOCOM
1996
IEEE
14 years 9 days ago
Maintaining High Throughput during Overload in ATM Switches
This report analyzes two popular heuristics for ensuring packet integrity in ATM switching systems. In particular, we analyze the behavior of packet tail discarding, in order to u...
Jonathan S. Turner
DAC
2010
ACM
14 years 2 days ago
Eyecharts: constructive benchmarking of gate sizing heuristics
—Discrete gate sizing is one of the most commonly used, flexible, and powerful techniques for digital circuit optimization. The underlying problem has been proven to be NP-hard ...
Puneet Gupta, Andrew B. Kahng, Amarnath Kasibhatla...
NN
2006
Springer
13 years 8 months ago
Speed-accuracy trade-off in planned arm movements with delayed feedback
The Vector Integration to Endpoint (VITE) circuit describes a real-time neural network model simulating behavioral and neurobiological properties of planned arm and hand movements...
Dan Beamish, I. Scott MacKenzie, Jianhong Wu
FPGA
2010
ACM
182views FPGA» more  FPGA 2010»
13 years 6 months ago
A comprehensive approach to modeling, characterizing and optimizing for metastability in FPGAs
Metastability is a phenomenon that can cause system failures in digital circuits. It may occur whenever signals are being transmitted across asynchronous or unrelated clock domain...
Doris Chen, Deshanand Singh, Jeffrey Chromczak, Da...