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ICCD
2004
IEEE
113views Hardware» more  ICCD 2004»
14 years 5 months ago
Toward an Integrated Design Methodology for Fault-Tolerant, Multiple Clock/Voltage Integrated Systems
Abstract - This paper describes a communicationcentric design methodology that addresses the fundamental challenges induced by the emergence of truly heterogeneous Systems-on-Chip ...
Radu Marculescu, Diana Marculescu, Larry T. Pilegg...
DAC
2009
ACM
14 years 9 months ago
Statistical reliability analysis under process variation and aging effects
Circuit reliability is affected by various fabrication-time and run-time effects. Fabrication-induced process variation has significant impact on circuit performance and reliabilit...
Yinghai Lu, Li Shang, Hai Zhou, Hengliang Zhu, Fan...
ISPD
2011
ACM
253views Hardware» more  ISPD 2011»
12 years 11 months ago
Assembling 2D blocks into 3D chips
Three-dimensional ICs promise to significantly extend the scale of system integration and facilitate new-generation electronics. However, progress in commercial 3D ICs has been s...
Johann Knechtel, Igor L. Markov, Jens Lienig
ASPDAC
2012
ACM
290views Hardware» more  ASPDAC 2012»
12 years 4 months ago
CODA: A concurrent online delay measurement architecture for critical paths
With technology scaling, integrated circuits behave more unpredictably due to process variation, environmental changes and aging effects. Various variation-aware and adaptive desi...
Yubin Zhang, Haile Yu, Qiang Xu
ICCAD
2001
IEEE
106views Hardware» more  ICCAD 2001»
14 years 5 months ago
A Layout-Aware Synthesis Methodology for RF Circuits
In this paper a layout-aware RF synthesis methodology is presented. The methodology combines the power of a differential evolution algorithm with cost function response modeling a...
Peter J. Vancorenland, Geert Van der Plas, Michiel...