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TCAD
2010
154views more  TCAD 2010»
13 years 3 months ago
Performance-Driven Dual-Rail Routing Architecture for Structured ASIC Design Style
In recent years, structured application-specific integrated circuit (ASIC) design style has lessened the importance of mask cost. Multiple structured ASIC chip designs share the sa...
Fu-Wei Chen, Yi-Yu Liu
FPGA
2011
ACM
393views FPGA» more  FPGA 2011»
12 years 11 months ago
Comparing FPGA vs. custom cmos and the impact on processor microarchitecture
As soft processors are increasingly used in diverse applications, there is a need to evolve their microarchitectures in a way that suits the FPGA implementation substrate. This pa...
Henry Wong, Vaughn Betz, Jonathan Rose
CIMCA
2006
IEEE
14 years 2 months ago
Computational Nanomechatronics: A Pathway for Control and Manufacturing Nanorobots
This paper describes an innovative work for nanorobot design and manufacturing, using a computer simulation and system on chip prototyping approach. The use of CMOS as integrated ...
Adriano Cavalcanti, Warren W. Wood, Luiz C. Kretly...
ICT
2004
Springer
178views Communications» more  ICT 2004»
14 years 1 months ago
BiCMOS Variable Gain LNA at C-Band with Ultra Low Power Consumption for WLAN
An ultra low power consuming low noise amplifier (LNA) at C-band with variable gain for adaptive antenna combining is presented in this paper. The microwave monolithic integrated c...
Frank Ellinger, C. Carta, L. Rodoni, G. von Bü...
DFT
1997
IEEE
101views VLSI» more  DFT 1997»
14 years 15 days ago
Crosstalk Minimization in Three-Layer HVH Channel Routing
Crosstalk has become a major issue in VLSI design due to the high frequency, long interconnecting lines and small spacing between interconnects in today's integrated circuits...
Zhan Chen, Israel Koren