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FPGA
2004
ACM
117views FPGA» more  FPGA 2004»
14 years 1 months ago
A magnetoelectronic macrocell employing reconfigurable threshold logic
In this paper, we introduce a reconfigurable fabric based around a new class of circuit element: the hybrid Hall effect (HHE) magnetoelectronic device. Because they incorporate a ...
Steve Ferrera, Nicholas P. Carter
ISVLSI
2002
IEEE
129views VLSI» more  ISVLSI 2002»
14 years 1 months ago
Accelerating Retiming Under the Coupled-Edge Timing Model
Retiming has been shown to be a powerful technique for improving the performance of synchronous circuits. However, even though retiming algorithms of polynomial time complexity ha...
Ingmar Neumann, Kolja Sulimma, Wolfgang Kunz
ICCAD
1993
IEEE
121views Hardware» more  ICCAD 1993»
14 years 10 days ago
Hierarchical extraction of 3D interconnect capacitances in large regular VLSI structures
For submicron integrated circuits, 3D numerical techniques are required to accurately compute the values of the interconnect capacitances. In this paper, we describe an hierarchic...
Arjan J. van Genderen, N. P. van der Meijs
HOST
2009
IEEE
13 years 12 months ago
New Design Strategy for Improving Hardware Trojan Detection and Reducing Trojan Activation Time
Hardware Trojans in integrated circuits and systems have become serious concern to fabless semiconductor industry and government agencies in recent years. Most of the previously p...
Hassan Salmani, Mohammad Tehranipoor, Jim Plusquel...
IPPS
2010
IEEE
13 years 5 months ago
Prototype for a large-scale static timing analyzer running on an IBM Blue Gene
This paper focuses on parallelization of the classic static timing analysis (STA) algorithm for verifying timing characteristics of digital integrated circuits. Given ever-increasi...
Akintayo Holder, Christopher D. Carothers, Kerim K...