Accelerating Retiming Under the Coupled-Edge Timing Model

Retiming has been shown to be a powerful technique for improving the performance of synchronous circuits. However, even though retiming algorithms of polynomial time complexity have been developed the runtimes still may become prohibitively long for large circuits. For the original FEAS algorithm proposed by Leiserson and Saxe, acceleration techniques have been developed solving this problem in practice. However, FEAS uses a simple circuit model being fairly inaccurate for gate level net lists mapped onto actual technologies. Recently a retiming algorithm FEAS_CTM based on a new timing model tackling this problem has been proposed. In this paper we present a technique for speeding up execution time of FEAS_CTM. This technique is also suitable for a variety of published algorithms based on the circuit model proposed by Soyata and Friedman. In this work the approach has been integrated into FEAS_CTM and its benefit has been proven by experimental results.

• Type: Conference
• Year: 2002
• Where: ISVLSI
• Authors: Ingmar Neumann, Kolja Sulimma, Wolfgang Kunz
• Keywords: Algorithms, Circuit Model, ISVLSI 2002, Polynomial Time Complexity, VLSI