259 search results - page 47 / 52 » Application-specific instruction generation for configurable... |
CGO
2003
IEEE
14 years 19 days ago
2003
IEEE
Predicated execution can eliminate hard to predict branches and help to enable instruction level parallelism. Many current predication variants exist where the result update is co...
DSN
2007
IEEE
13 years 11 months ago
2007
IEEE
Although there are various ways to exploit software vulnerabilities for malicious attacks, the attacks always result in unexpected behavior in program execution, deviating from wh...
DAC
2003
ACM
14 years 8 months ago
2003
ACM
The capability of performing architectural exploration has become essential for embedded microprocessor design in System-On-Chip. While many retargetable instruction set (ISA) sim...
ICASSP
2008
IEEE
14 years 1 months ago
2008
IEEE
Multiple memory banks design is employed in many high performance DSP processors. This architectural feature supports higher memory bandwidth by allowing multiple data memory acce...
LCTRTS
1999
Springer
13 years 11 months ago
1999
Springer
A Zero Overhead Loop Buffer (ZOLB) is an architectural feature that is commonly found in DSP processors. This buffer can be viewed as a compiler managed cache that contains a sequ...