Don't-care conditions provide additional flexibility in logic synthesis and optimization. However, most work only focuses on the gate level because it is difficult to handle ...
This paper presents a formal language for the design of component-based enterprise system. The language (StAC) allows the usual parallel and sequential behaviours, but most signifi...
Timed and weak timed simulation relations are often used to show that operations on hybrid systems result in equivalent behavior or in conservative overapproximations. Given that s...
Abstract. This paper shows that we can take advantage of information about the probabilities of the occurrences of events, when this information is available, to refine the classic...
Propositional satisfiability solving, or SAT, is an important reasoning task arising in numerous applications, such as circuit design, formal verification, planning, scheduling or...