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CAV
2004
Springer
111views Hardware» more  CAV 2004»
14 years 24 days ago
Using Interface Refinement to Integrate Formal Verification into the Design Cycle
Jacob Chang, Sergey Berezin, David L. Dill
ACSW
2006
13 years 8 months ago
Formal analysis of secure contracting protocol for e-tendering
Formal specification and verification of protocols have been credited for uncovering protocol flaws; revealing inadequacies in protocol design of the Initial Stage and Negotiation...
Rong Du, Ernest Foo, Colin Boyd, Kim-Kwang Raymond...
LARCH
1992
13 years 11 months ago
Using Transformations and Verification in Circuit Design
James B. Saxe, John V. Guttag, James J. Horning, S...
ICCS
2007
Springer
13 years 11 months ago
Formal Verification of Analog and Mixed Signal Designs in Mathematica
In this paper, we show how symbolic algebra in Mathematica can be used to formally verify analog and mixed signal designs. The verification methodology is based on combining induct...
Mohamed H. Zaki, Ghiath Al Sammane, Sofiène...
ISCAS
2003
IEEE
135views Hardware» more  ISCAS 2003»
14 years 20 days ago
Formal verification of LTL formulas for SystemC designs
To handle today’s complexity, modern circuits and systems be specified at a high level of abstraction. Recently, SystemC has been proposed as a language that allows a fast on o...
Daniel Große, Rolf Drechsler