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FMCAD
2007
Springer
13 years 11 months ago
2007
Springer
We present a framework for formal verification of embedded custom memories. Memory verification is complicated ifficulty in abstracting design parameters induced by the inherently ...
TELSYS
2002
13 years 7 months ago
2002
Formal description techniques, verification methods, and their tool-based automated application meanwhile provide valuable support for the formal analysis of communication protocol...
SAFECOMP
2010
Springer
13 years 5 months ago
2010
Springer
Formal verification efforts in the area of robotics are still comparatively scarce. In this paper we report on our experiences with one such effort, which was concerned with design...
ICCAD
1994
IEEE
13 years 11 months ago
1994
IEEE
Language containment is a method for design verification that involves checking if the behavior of the system to be verified is a subset of the behavior of the specifications (pro...
CORR
2008
Springer
13 years 7 months ago
2008
Springer
Synchronous languages rely on formal methods to ease the development of applications in an efficient and reusable way. Formal methods have been advocated as a means of increasing t...