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» Approximate logic synthesis for error tolerant applications
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SARA
2009
Springer
14 years 4 months ago
Automated Redesign with the General Redesign Engine
: Given a system design (SD), a key task is to optimize this design to reduce the probability of catastrophic failures. We consider the task of redesigning an SD to minimize the pr...
Alexander Feldman, Gregory M. Provan, Johan de Kle...
DFT
1999
IEEE
114views VLSI» more  DFT 1999»
14 years 2 months ago
Yield Enhancement Considerations for a Single-Chip Multiprocessor System with Embedded DRAM
A programmable single-chip multiprocessor system for video coding has been developed. The system is implemented in a high-performance 0.25 m logic/embedded DRAM process. It integr...
Markus Rudack, Dirk Niggemeyer
PLDI
2006
ACM
14 years 3 months ago
DieHard: probabilistic memory safety for unsafe languages
Applications written in unsafe languages like C and C++ are vulnerable to memory errors such as buffer overflows, dangling pointers, and reads of uninitialized data. Such errors ...
Emery D. Berger, Benjamin G. Zorn
GIS
2006
ACM
13 years 9 months ago
Qualitative polyline similarity testing with applications to query-by-sketch, indexing and classification
We present an algorithm for polyline (and polygon) similarity testing that is based on the double-cross formalism. To determine the degree of similarity between two polylines, the...
Bart Kuijpers, Bart Moelans, Nico Van de Weghe
SIBGRAPI
2006
IEEE
14 years 3 months ago
Polygonization of volumetric reconstructions from silhouettes
In this work we propose a method for the polygonization of octree-based reconstructions by dual contouring. Dual contouring is an adaptive method for determining contiguous polygo...
Anselmo Antunes Montenegro, Luiz Velho, Paulo Ceza...