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GLVLSI
2005
IEEE
132views VLSI» more  GLVLSI 2005»
14 years 2 months ago
FPGA implementation of a modular and pipelined WF scheduler for high speed OC192 networks
In this paper we propose an FPGA implementation of a multi protocol Weighted Fair (WF) queuing algorithm able to handle variable length packets targeted for Packet Over Sonet (POS...
Abdallah Merhebi, Otmane Aït Mohamed
ASPDAC
2005
ACM
111views Hardware» more  ASPDAC 2005»
13 years 10 months ago
Wave-pipelined on-chip global interconnect
— A novel wave-pipelined global interconnect system is developed for reliable, high throughput, on-chip data communication. We argue that because there is only a single signal pr...
Lizheng Zhang, Yuhen Hu, Charlie Chung-Ping Chen
SENSYS
2005
ACM
14 years 2 months ago
Intelligent light control using sensor networks
Increasing user comfort and reducing operation costs have always been two primary objectives of building operations and control strategies. Current building control strategies are...
Vipul Singhvi, Andreas Krause, Carlos Guestrin, Ja...
CCGRID
2006
IEEE
14 years 2 months ago
Component-Based Modeling, Analysis and Animation
Component-based software construction is widely used in a variety of applications, from embedded environments to grid computing. However, errors in these applications and systems ...
Jeff Kramer
CODES
2007
IEEE
14 years 3 months ago
Thread warping: a framework for dynamic synthesis of thread accelerators
We present a dynamic optimization technique, thread warping, that uses a single processor on a multiprocessor system to dynamically synthesize threads into custom accelerator circ...
Greg Stitt, Frank Vahid