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SDL
2003
147views Hardware» more  SDL 2003»
13 years 9 months ago
Modelling and Evaluation of a Network on Chip Architecture Using SDL
Network on Chip (NoC) is a new paradigm for designing large and complex systems on chips (SoCs). In this paradigm, a packet switched network is provided for on-chip communication. ...
Rickard Holsmark, Magnus Högberg, Shashi Kuma...
ARC
2009
Springer
188views Hardware» more  ARC 2009»
14 years 2 months ago
Word-Length Optimization and Error Analysis of a Multivariate Gaussian Random Number Generator
Abstract. Monte Carlo simulation is one of the most widely used techniques for computationally intensive simulations in mathematical analysis and modeling. A multivariate Gaussian ...
Chalermpol Saiprasert, Christos-Savvas Bouganis, G...
SIGCOMM
2004
ACM
14 years 1 months ago
Work-conserving distributed schedulers for Terabit routers
−Buffered multistage interconnection networks offer one of the most scalable and cost-effective approaches to building high capacity routers. Unfortunately, the performance of su...
Prashanth Pappu, Jonathan S. Turner, Kenneth Wong
JUCS
2010
89views more  JUCS 2010»
13 years 6 months ago
Towards a Virtual Trusted Platform
: The advances and adoption of Trusted Computing and hardware assisted virtualisation technologies in standard PC platforms promise new approaches in building a robust virtualisati...
Martin Pirker, Ronald Toegl
AAAI
2010
13 years 9 months ago
Toward an Architecture for Never-Ending Language Learning
We consider here the problem of building a never-ending language learner; that is, an intelligent computer agent that runs forever and that each day must (1) extract, or read, inf...
Andrew Carlson, Justin Betteridge, Bryan Kisiel, B...