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» Architectural Considerations for Energy Efficiency
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TCOS
2010
13 years 3 months ago
Green Secure Processors: Towards Power-Efficient Secure Processor Design
With the increasing wealth of digital information stored on computer systems today, security issues have become increasingly important. In addition to attacks targeting the softwar...
Siddhartha Chhabra, Yan Solihin
FCCM
2009
IEEE
192views VLSI» more  FCCM 2009»
14 years 3 months ago
FPGA Floating Point Datapath Compiler
This paper will describe the architecture of a compiler which will convert an untimed C description of a set of floating point expressions into a synthesizable datapath optimized ...
Martin Langhammer, Tom VanCourt
DAC
2001
ACM
14 years 9 months ago
A2BC: Adaptive Address Bus Coding for Low Power Deep Sub-Micron Designs
Due to larger buses (length, width) and deep sub-micron effects where coupling capacitances between bus lines are in the same order of magnitude as base capacitances, power consum...
Haris Lekatsas, Jörg Henkel
SENSYS
2004
ACM
14 years 1 months ago
Power - time optimal algorithm for computing FFT over sensor networks
bstract: Power - Time Optimal Algorithm for Computing FFT over Sensor Networks Categories and Subject Descriptors C.2.1 [Network Architecture and Design] Wireless Communication, Di...
Turkmen Canli, Mark Terwilliger, Ajay K. Gupta, As...
TPDS
2002
105views more  TPDS 2002»
13 years 8 months ago
HiPER: A Compact Narrow Channel Router with Hop-by-Hop Error Correction
Multiprocessor architectures demand efficient interprocessor communication to maximize system utilization and performance. To meet future demands, these interconnects must communic...
Phil May, Santithorn Bunchua, D. Scott Wills