Sciweavers

180 search results - page 21 / 36
» Architectural Specification, Exploration and Simulation Thro...
Sort
View
TSE
2002
122views more  TSE 2002»
13 years 7 months ago
Virtual Benchmarking and Model Continuity in Prototyping Embedded Multiprocessor Signal Processing Systems
The complexity of hardware/software codesign of embedded real-time signal processing systems can be reduced by rapid system prototyping (RSP). However, existing RSP frameworks do n...
Randall S. Janka, Linda M. Wills, Lewis B. Baumsta...
ISCA
2009
IEEE
189views Hardware» more  ISCA 2009»
14 years 2 months ago
Hybrid cache architecture with disparate memory technologies
Caching techniques have been an efficient mechanism for mitigating the effects of the processor-memory speed gap. Traditional multi-level SRAM-based cache hierarchies, especially...
Xiaoxia Wu, Jian Li, Lixin Zhang, Evan Speight, Ra...
ADHOC
2008
88views more  ADHOC 2008»
13 years 7 months ago
Safari: A self-organizing, hierarchical architecture for scalable ad hoc networking
As wireless devices become more pervasive, mobile ad hoc networks are gaining importance, motivating the development of highly scalable ad hoc networking techniques. In this paper...
Shu Du, Ahamed Khan, Santashil PalChaudhuri, Ansle...
ICMCS
1996
IEEE
104views Multimedia» more  ICMCS 1996»
13 years 11 months ago
Design and Performance Tradeoffs in Clustered Video Servers
In this paper, we investigate the suitability of clustered architectures for designing scalable multimedia servers. Specifically, we evaluate the effects of: (i) architectural des...
Renu Tewari, Rajat Mukherjee, Daniel M. Dias, Harr...
DAC
2011
ACM
12 years 7 months ago
Synchronous sequential computation with molecular reactions
Just as electronic systems implement computation in terms of voltage (energy per unit charge), molecular systems compute in terms of chemical concentrations (molecules per unit vo...
Hua Jiang, Marc D. Riedel, Keshab K. Parhi