558 search results - page 112 / 112 » Architectural Style - Based Modeling and Simulation of Compl... |
147
Voted
IEEEPACT
2006
IEEE
15 years 8 months ago
2006
IEEE
As chip multiprocessors (CMPs) become increasingly mainstream, architects have likewise become more interested in how best to share a cache hierarchy among multiple simultaneous t...
101
Voted
MICRO
2009
IEEE
15 years 9 months ago
2009
IEEE
Transactional Memory aims to provide a programming model that makes parallel programming easier. Hardware implementations of transactional memory (HTM) suffer from fewer overhead...
132
Voted
HPDC
2000
IEEE
15 years 7 months ago
2000
IEEE
To provide Quality of Service (QoS) guarantee in distributed services, it is necessary to reserve multiple computing and communication resources for each service session. Meanwhile...