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FPGA
2009
ACM
201views FPGA» more  FPGA 2009»
14 years 2 months ago
A high-performance FPGA architecture for restricted boltzmann machines
Despite the popularity and success of neural networks in research, the number of resulting commercial or industrial applications have been limited. A primary cause of this lack of...
Daniel L. Ly, Paul Chow
INFOCOM
1998
IEEE
13 years 11 months ago
MSOCKS: An Architecture for Transport Layer Mobility
Mobile nodes of the future will be equiped with multiple network interfaces to take advantage of overlay networks, yet no current mobility systems provide full support for the sim...
David A. Maltz, Pravin Bhagwat
HICSS
1996
IEEE
136views Biometrics» more  HICSS 1996»
13 years 11 months ago
Design of a Real-Time Co-Operating System for Multiprocessor Workstations
: We have designed a Real-Time Co-Operating System (RTCOS) for simultaneously supporting real-time and non-real-time activities on a workstation with two or more processors. The RT...
Gebran Krikor, Md. Touhidur Raza, David B. Stewart
ISCA
1997
IEEE
108views Hardware» more  ISCA 1997»
13 years 11 months ago
The SGI Origin: A ccNUMA Highly Scalable Server
The SGI Origin 2000 is a cache-coherent non-uniform memory access (ccNUMA) multiprocessor designed and manufactured by Silicon Graphics, Inc. The Origin system was designed from t...
James Laudon, Daniel Lenoski
IISWC
2009
IEEE
14 years 2 months ago
Understanding PARSEC performance on contemporary CMPs
PARSEC is a reference application suite used in industry and academia to assess new Chip Multiprocessor (CMP) designs. No investigation to date has profiled PARSEC on real hardwa...
Major Bhadauria, Vincent M. Weaver, Sally A. McKee