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PPOPP
2010
ACM
14 years 1 months ago
Thread to strand binding of parallel network applications in massive multi-threaded systems
In processors with several levels of hardware resource sharing, like CMPs in which each core is an SMT, the scheduling process becomes more complex than in processors with a singl...
Petar Radojkovic, Vladimir Cakarevic, Javier Verd&...
VLSID
2008
IEEE
166views VLSI» more  VLSID 2008»
14 years 7 months ago
Exploring the Processor and ISA Design for Wireless Sensor Network Applications
Power consumption, physical size, and architecture design of sensor node processors have been the focus of sensor network research in the architecture community. What lies at the ...
Shashidhar Mysore, Banit Agrawal, Frederic T. Chon...
ANCS
2005
ACM
14 years 29 days ago
Framework for supporting multi-service edge packet processing on network processors
Network edge packet-processing systems, as are commonly implemented on network processor platforms, are increasingly required to support a rich set of services. These multi-servic...
Arun Raghunath, Aaron R. Kunze, Erik J. Johnson, V...
DATE
2003
IEEE
108views Hardware» more  DATE 2003»
14 years 20 days ago
Comparing Analytical Modeling with Simulation for Network Processors: A Case Study
Programming network processors remains an art due to the variety of different network processor architectures and due to little support to reason and explore implementations on su...
Matthias Gries, Chidamber Kulkarni, Christian Saue...
IPPS
2000
IEEE
13 years 11 months ago
Support for Recoverable Memory in the Distributed Virtual Communication Machine
The Distributed Virtual Communication Machine (DVCM) is a software communication architecture for clusters of workstations equipped with programmable network interfaces (NIs) for ...
Marcel-Catalin Rosu, Karsten Schwan