Abstract--Reservation Tables (RTs) have long been used to detect conflicts between operations that simultaneously access the same architectural resource. Traditionally, these RTs h...
Peter Grun, Ashok Halambi, Nikil D. Dutt, Alexandr...
This paper explores hardware-implemented error-detection and security mechanisms embedded as modules in a hardware-level framework called the Reliability and Security Engine (RSE)...
Nithin Nakka, Zbigniew Kalbarczyk, Ravishankar K. ...
Multiprocessor architectures that continuously execute atomic blocks (or chunks) of instructions can improve performance and software productivity. However, all of the prior propo...
— Widespread deployment of Wi-Fi together with 3G upgrades to cellular networks is rapidly creating areas where multiple wireless IP technologies are accessible. WiMAX will furth...
Kyriakos Manousakis, Praveen Gopalakrishnan, Dave ...
Heterogeneous multi-core processors, such as the IBM Cell processor, can deliver high performance. However, these processors are notoriously difficult to program: different cores...