Sciweavers

255 search results - page 4 / 51
» Architectural Support for Synchronous Task Communication
Sort
View
CF
2010
ACM
14 years 16 days ago
On-chip communication and synchronization mechanisms with cache-integrated network interfaces
Per-core local (scratchpad) memories allow direct inter-core communication, with latency and energy advantages over coherent cache-based communication, especially as CMP architect...
Stamatis G. Kavadias, Manolis Katevenis, Michail Z...
CCGRID
2009
IEEE
14 years 2 months ago
Natively Supporting True One-Sided Communication in
As high-end computing systems continue to grow in scale, the performance that applications can achieve on such large scale systems depends heavily on their ability to avoid explic...
Gopalakrishnan Santhanaraman, Pavan Balaji, K. Gop...
ICPPW
2006
IEEE
14 years 1 months ago
A Scalable Synchronization Technique for Distributed Virtual Environments Based on Networked-Server Architectures
In recent years, large scale distributed virtual environments have become a major trend in distributed applications, mainly due to the enormous popularity of multiplayer online ga...
Pedro Morillo, Juan M. Orduña, José ...
MICRO
2010
IEEE
149views Hardware» more  MICRO 2010»
13 years 5 months ago
ReMAP: A Reconfigurable Heterogeneous Multicore Architecture
This paper presents ReMAP, a reconfigurable architecture geared towards accelerating and parallelizing applications within a heterogeneous CMP. In ReMAP, threads share a common rec...
Matthew A. Watkins, David H. Albonesi
NOCS
2009
IEEE
14 years 2 months ago
Comparing tightly and loosely coupled mesochronous synchronizers in a NoC switch architecture
With the advent of Networks-on-Chip (NoCs), the interest for mesochronous synchronizers is again on the rise due to the intricacies of skew-controlled chip-wide clock tree distrib...
Daniele Ludovici, Alessandro Strano, Davide Bertoz...