NOCS 2009 - PDF Preprint Papers

NOCS 2009 International Symposium on Networks-on-Chip

Teaser Browsing | Click Here

Title Browsing | Click Here

Wall of Fame | Most Viewed NOCS-2009 Paper

click to vote

NOCS
2009
IEEE

197views Computer Networks» more NOCS 2009»

Comparing tightly and loosely coupled mesochronous synchronizers in a NoC switch architecture

14 years 6 months ago

Download ce.et.tudelft.nl

With the advent of Networks-on-Chip (NoCs), the interest for mesochronous synchronizers is again on the rise due to the intricacies of skew-controlled chip-wide clock tree distrib...

Daniele Ludovici, Alessandro Strano, Davide Bertoz...

claim paper

Read More »

Disclaimer and Copyright Notice

Sciweavers respects the rights of all copyright holders and in this regard, authors are only allowed to share a link to their preprint paper on their own website. Every contribution is associated with a desciptive image. It is the sole responsibility of the authors to ensure that their posted image is not copyright infringing. This service is compliant with IEEE copyright.

Id	Views	Title	Status

1	197	Comparing tightly and loosely coupled mesochronous synchronizers in a NoC switch architecture	claim
2	160	CTC: An end-to-end flow control protocol for multi-core systems-on-chip	claim
3	152	HiRA: A methodology for deadlock free routing in hierarchical networks on chip	claim
4	151	A modular synchronizing FIFO for NoCs	claim
5	135	Best of both worlds: A bus enhanced NoC (BENoC)	claim
6	133	Networks-on-chip in emerging interconnect paradigms: Advantages and challenges	claim
7	132	Scalability of network-on-chip communication architecture for 3-D meshes	claim
8	109	Analysis of photonic networks for a chip multiprocessor using scientific applications	claim
9	108	A GALS many-core heterogeneous DSP platform with source-synchronous on-chip interconnection network	claim
10	104	Packet-level static timing analysis for NoCs	claim
11	103	Static virtual channel allocation in oblivious routing	claim
12	97	Silicon-photonic clos networks for global on-chip communication	claim
13	95	Estimating reliability and throughput of source-synchronous wave-pipelined interconnect	claim
14	89	Flow-aware allocation for on-chip networks	claim
15	83	Dynamic packet fragmentation for increased virtual channel utilization in on-chip routers	claim
16	83	Exploring concentration and channel slicing in on-chip network router	claim
17	78	Energy efficient application mapping to NoC processing elements operating at multiple voltage levels	claim

Sciweavers

Explore & Download

Productivity Tools

Document Tools

Image Tools

Sciweavers