159 search results - page 10 / 32 » Architectural Synthesis of Timed Asynchronous Systems |
FMICS
2006
Springer
14 years 8 days ago
2006
Springer
Abstract. The design flow of systems-on-a-chip (SoCs) identifies several abstraction levels higher than the Register-Transfer-Level that constitutes the input of the synthesis tool...
CORR
2006
Springer
13 years 8 months ago
2006
Springer
We introduce a new approach to take into account the memory architecture and the memory mapping in the High- Level Synthesis of Real-Time embedded systems. We formalize the memory...
ASYNC
2004
IEEE
14 years 10 days ago
2004
IEEE
This paper presents a decomposition method for speedindependent circuit design that is capable of significantly reducing the cost of synthesis. In particular, this method synthesi...
ASPDAC
2005
ACM
13 years 10 months ago
2005
ACM
- To date, most high-level synthesis systems do not automatically solve present design problems, such as those related to timing associated with the physical implementation of mult...
FPL
2007
Springer
14 years 2 months ago
2007
Springer
Today’s heterogeneous embedded systems combine components from different domains, such as software, analogue hardware and digital hardware. The design and implementation of thes...