Sciweavers

271 search results - page 37 / 55
» Architectural dependability evaluation with Arcade
Sort
View
MICRO
1995
IEEE
102views Hardware» more  MICRO 1995»
13 years 11 months ago
Zero-cycle loads: microarchitecture support for reducing load latency
Untolerated load instruction latencies often have a significant impact on overall program performance. As one means of mitigating this effect, we present an aggressive hardware-b...
Todd M. Austin, Gurindar S. Sohi
SIGMOD
2009
ACM
161views Database» more  SIGMOD 2009»
14 years 2 months ago
Dependency-aware reordering for parallelizing query optimization in multi-core CPUs
The state of the art commercial query optimizers employ cost-based optimization and exploit dynamic programming (DP) to find the optimal query execution plan (QEP) without evalua...
Wook-Shin Han, Jinsoo Lee
MICRO
2006
IEEE
135views Hardware» more  MICRO 2006»
14 years 1 months ago
Support for High-Frequency Streaming in CMPs
As the industry moves toward larger-scale chip multiprocessors, the need to parallelize applications grows. High inter-thread communication delays, exacerbated by over-stressed hi...
Ram Rangan, Neil Vachharajani, Adam Stoler, Guilhe...
INTELLCOMM
2004
Springer
14 years 24 days ago
About the Heterogeneity of Web Prefetching Performance Key Metrics
Web prefetching techniques have pointed to be especially important to reduce web latencies and, consequently, an important set of works can be found in the open literature. But, in...
Josep Domènech, Julio Sahuquillo, Jos&eacut...
ICML
2003
IEEE
14 years 8 months ago
Hidden Markov Support Vector Machines
This paper presents a novel discriminative learning technique for label sequences based on a combination of the two most successful learning algorithms, Support Vector Machines an...
Yasemin Altun, Ioannis Tsochantaridis, Thomas Hofm...