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» Architectural descriptions for FPGA circuits
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FPGA
2001
ACM
137views FPGA» more  FPGA 2001»
14 years 2 hour ago
A crosstalk-aware timing-driven router for FPGAs
As integrated circuits are migrated to more advanced technologies, it has become clear that crosstalk is an important physical phenomenon that must be taken into account. Crosstal...
Steven J. E. Wilton
IEICET
2008
124views more  IEICET 2008»
13 years 7 months ago
A Secure Content Delivery System Based on a Partially Reconfigurable FPGA
We developed a content delivery system using a partially reconfigurable FPGA to securely distribute digital content on the Internet. With partial reconfigurability of a Xilinx Vir...
Yohei Hori, Hiroyuki Yokoyama, Hirofumi Sakane, Ke...
GLVLSI
2008
IEEE
197views VLSI» more  GLVLSI 2008»
13 years 7 months ago
Efficient tree topology for FPGA interconnect network
This paper presents an improved Tree-based architecture that unifies two unidirectional programmable networks: A predictible downward network based on the Butterfly-FatTree topolo...
Zied Marrakchi, Hayder Mrabet, Emna Amouri, Habib ...
VLSID
2007
IEEE
153views VLSI» more  VLSID 2007»
14 years 7 months ago
Extracting Logic Circuit Structure from Conjunctive Normal Form Descriptions
Boolean Satisfiability is seeing increasing use as a decision procedure in Electronic Design Automation (EDA) and other domains. Most applications encode their domain specific cons...
Zhaohui Fu, Sharad Malik
ISLPED
2004
ACM
169views Hardware» more  ISLPED 2004»
14 years 28 days ago
Delay optimal low-power circuit clustering for FPGAs with dual supply voltages
This paper presents a delay optimal FPGA clustering algorithm targeting low power. We assume that the configurable logic blocks of the FPGA can be programmed using either a high s...
Deming Chen, Jason Cong