110 search results - page 10 / 22 » Architectural simulation for a programmable DSP chip set |
CCECE
2006
IEEE
14 years 1 months ago
2006
IEEE
Real Time embedded system designers are facing extreme challenges in underlying architectural design selection. It involves the selection of a programmable, concurrent, heterogene...
VMV
2001
13 years 8 months ago
2001
In this paper we demonstrate the benefits of the most current nVidia graphics chip set for realistic simulation and rendering of dynamic water surfaces in real-time. In particular...
JSA
2007
13 years 7 months ago
2007
Mapping of applications on a Multiprocessor System-on-Chip (MP-SoC) is a crucial step to optimize performance, energy and memory constraints at the same time. The problem is formu...
CAL
2006
13 years 7 months ago
2006
Multiple core designs have become commonplace in the processor market, and are hence a major focus in modern computer architecture research. Thus, for both product development and ...
IPPS
2003
IEEE
14 years 20 days ago
2003
IEEE
Tiled architectures can provide a model for early estimation of global interconnect costs. A design exploration tool for reconfigurable architectures is currently under developmen...