85 search results - page 15 / 17 » Architectural support for shadow memory in multiprocessors |
HPCA
2006
IEEE
14 years 7 months ago
2006
IEEE
Transactional memory (TM) simplifies parallel programming by guaranteeing that transactions appear to execute atomically and in isolation. Implementing these properties includes p...
HPCA
1998
IEEE
13 years 11 months ago
1998
IEEE
Scalable shared-memory multiprocessors that are designed as Cache-Only Memory Architectures Coma allow automatic replication and migration of data in the main memory. This enhance...
IISWC
2009
IEEE
14 years 2 months ago
2009
IEEE
PARSEC is a reference application suite used in industry and academia to assess new Chip Multiprocessor (CMP) designs. No investigation to date has profiled PARSEC on real hardwa...
SC
1995
ACM
13 years 11 months ago
1995
ACM
This paper presents techniques for compiling loops with complex, indirect array accesses into loops whose array references have at most one level of indirection. The transformatio...
IPPS
1998
IEEE
13 years 11 months ago
1998
IEEE
We are developing a compiler that translates ordinary MATLAB scripts into code suitable for compilation and execution on parallel computers supporting C and the MPI message-passin...