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DSN
2006
IEEE
14 years 1 months ago
Automatic Instruction-Level Software-Only Recovery
As chip densities and clock rates increase, processors are becoming more susceptible to transient faults that can affect program correctness. Computer architects have typically ad...
Jonathan Chang, George A. Reis, David I. August
DFT
2003
IEEE
142views VLSI» more  DFT 2003»
14 years 24 days ago
Exploiting Instruction Redundancy for Transient Fault Tolerance
This paper presents an approach for integrating fault-tolerance techniques into microprocessors by utilizing instruction redundancy as well as time redundancy. Smaller and smaller...
Toshinori Sato
ICS
2007
Tsinghua U.
14 years 1 months ago
Proactive fault tolerance for HPC with Xen virtualization
Large-scale parallel computing is relying increasingly on clusters with thousands of processors. At such large counts of compute nodes, faults are becoming common place. Current t...
Arun Babu Nagarajan, Frank Mueller, Christian Enge...
ICCS
2005
Springer
14 years 1 months ago
Super-Scalable Algorithms for Computing on 100, 000 Processors
In the next five years, the number of processors in high-end systems for scientific computing is expected to rise to tens and even hundreds of thousands. For example, the IBM Blu...
Christian Engelmann, Al Geist
CCGRID
2003
IEEE
14 years 24 days ago
Improved Read Performance in a Cost-Effective, Fault-Tolerant Parallel Virtual File System (CEFT-PVFS)
Due to the ever-widening performance gap between processors and disks, I/O operations tend to become the major performance bottleneck of data-intensive applications on modern clus...
Yifeng Zhu, Hong Jiang, Xiao Qin, Dan Feng, David ...