113 search results - page 20 / 23 » Architectural-Level Fault Tolerant Computation in Nanoelectr... |
ASPLOS
2009
ACM
14 years 8 months ago
2009
ACM
Future processors are expected to observe increasing rates of hardware faults. Using Dual-Modular Redundancy (DMR), two cores of a multicore can be loosely coupled to redundantly ...
IPPS
1998
IEEE
13 years 11 months ago
1998
IEEE
A real-time system must execute functionally correct computations in a timely manner. In order to guarantee that all tasks accepted in the system will meet their timing requiremen...
CCGRID
2010
IEEE
13 years 8 months ago
2010
IEEE
Fault tolerance will be a fundamental imperative in the next decade as machines containing hundreds of thousands of cores will be installed at various locations. In this context, ...
HPCA
2007
IEEE
14 years 7 months ago
2007
IEEE
This paper evaluates the suitability of the MapReduce model for multi-core and multi-processor systems. MapReduce was created by Google for application development on data-centers...
INFOCOM
2009
IEEE
14 years 2 months ago
2009
IEEE
—In hop-by-hop networks, provision of multipath routes for all nodes can improve fault tolerance and performance. In this paper we study the multipath route calculation by constr...