113 search results - page 21 / 23 » Architectural-Level Fault Tolerant Computation in Nanoelectr... |
EURONGI
2006
Springer
13 years 11 months ago
2006
Springer
Wireless sensor networks (WSNs) pose challenges not present in classical distributed systems: resource limitations, high failure rates, and ad hoc deployment. The lossy nature of w...
IEEEPACT
2007
IEEE
14 years 1 months ago
2007
IEEE
Under current worst-case design practices, manufacturers specify conservative values for processor frequencies in order to guarantee correctness. To recover some of the lost perfo...
CONCURRENCY
2010
13 years 7 months ago
2010
Over the past decade the number of processors in the high performance facilities went up to hundreds of thousands. As a direct consequence, while the computational power follow th...
TC
2011
13 years 2 months ago
2011
—CMOS scaling has long been a source of dramatic performance gains. However, semiconductor feature size reduction has resulted in increasing levels of operating temperatures and ...
DSN
2007
IEEE
14 years 1 months ago
2007
IEEE
Aggressive CMOS scaling will make future chip multiprocessors (CMPs) increasingly susceptible to transient faults, hard errors, manufacturing defects, and process variations. Exis...