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ARVLSI
1995
IEEE
78views VLSI» more  ARVLSI 1995»
14 years 2 months ago
A technique for high-speed, fine-resolution pattern generation and its CMOS implementation
This paper presents an architecture for generating a high-speed data pattern with precise edge placement resolution by using the matched delay technique. The technique involves ...
Gary C. Moyer, Mark Clements, Wentai Liu, Toby Sch...
SERA
2010
Springer
13 years 9 months ago
The Software Modeling and Implementation of Reliable Server Pooling and RSPLIB
Abstract—With the growing complexity of software applications, there is an increasing demand for solutions to distribute workload into server pools. Grid Computing provides power...
Xing Zhou, Thomas Dreibholz, Martin Becke, Jobin P...
CODES
2007
IEEE
14 years 5 months ago
Performance and resource optimization of NoC router architecture for master and slave IP cores
System-on-Chip architectures incorporate several IP cores with well defined master and slave characteristics in terms of on-chip communication. The paper presents a parameterized ...
Glenn Leary, Krishna Mehta, Karam S. Chatha
ICMCS
1996
IEEE
104views Multimedia» more  ICMCS 1996»
14 years 3 months ago
Design and Performance Tradeoffs in Clustered Video Servers
In this paper, we investigate the suitability of clustered architectures for designing scalable multimedia servers. Specifically, we evaluate the effects of: (i) architectural des...
Renu Tewari, Rajat Mukherjee, Daniel M. Dias, Harr...
GLVLSI
2008
IEEE
197views VLSI» more  GLVLSI 2008»
13 years 11 months ago
Efficient tree topology for FPGA interconnect network
This paper presents an improved Tree-based architecture that unifies two unidirectional programmable networks: A predictible downward network based on the Butterfly-FatTree topolo...
Zied Marrakchi, Hayder Mrabet, Emna Amouri, Habib ...