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JSS
2007
75views more  JSS 2007»
13 years 9 months ago
A rationale-based architecture model for design traceability and reasoning
Large systems often have a long life-span and comprise many intricately related elements. The verification and maintenance of these systems require a good understanding of their ...
Antony Tang, Yan Jin, Jun Han
GLVLSI
2005
IEEE
132views VLSI» more  GLVLSI 2005»
14 years 3 months ago
FPGA implementation of a modular and pipelined WF scheduler for high speed OC192 networks
In this paper we propose an FPGA implementation of a multi protocol Weighted Fair (WF) queuing algorithm able to handle variable length packets targeted for Packet Over Sonet (POS...
Abdallah Merhebi, Otmane Aït Mohamed
JSS
2007
109views more  JSS 2007»
13 years 9 months ago
Using Bayesian belief networks for change impact analysis in architecture design
Research into design rationale in the past has focused on argumentation-based design deliberations. These approaches cannot be used to support change impact analysis effectively ...
Antony Tang, Ann E. Nicholson, Yan Jin, Jun Han
ICPP
1993
IEEE
14 years 2 months ago
Dependence Analysis and Architecture Design for Bit-Level Algorithms
:. In designing application-specific bit-level architectures and in programming existing bit-level processor arrays, it is necessary to expand a word-level algorithm into its bit-...
Weijia Shang, Benjamin W. Wah
ITNG
2007
IEEE
14 years 4 months ago
On Design and Analysis of a Feasible Network-on-Chip (NoC) Architecture
In this paper, we present several enhanced network techniques which are appropriate for VLSI implementation and have reduced complexity, high throughput, and simple routing algori...
Jun Ho Bahn, Seung Eun Lee, Nader Bagherzadeh