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CC
2007
Springer
126views System Software» more  CC 2007»
14 years 4 months ago
An Array Allocation Scheme for Energy Reduction in Partitioned Memory Architectures
This paper presents a compiler technique that reduces the energy consumption of the memory subsystem, for an off-chip partitioned memory architecture having multiple memory banks ...
K. Shyam, R. Govindarajan
ADL
1998
Springer
178views Digital Library» more  ADL 1998»
14 years 2 months ago
Distributed Digital Library Architecture Incorporating Different Index Styles
The New Zealand Digital Library offers several collections of information over the World Wide Web. Although fulltext indexing is the primary access mechanism, musical collections ...
Rodger J. McNab, Ian H. Witten, Stefan J. Boddie
CSB
2004
IEEE
123views Bioinformatics» more  CSB 2004»
14 years 1 months ago
A New Hardware Architecture for Genomic and Proteomic Sequence Alignment
We describe a novel hardware architecture for genomic and proteomic sequence alignment which achieves a speed-up of two to three orders of magnitude over Smith-Waterman dynamic pr...
Greg Knowles, Paul Gardner-Stephen
ISCA
1993
IEEE
137views Hardware» more  ISCA 1993»
14 years 2 months ago
Architectural Support for Translation Table Management in Large Address Space Machines
Virtual memoy page translation tables provide mappings from virtual to physical addresses. When the hardware controlled Tratmlation L.ookaside Buffers (TLBs) do not contain a tran...
Jerome C. Huck, Jim Hays
CODES
2009
IEEE
13 years 11 months ago
A scalable parallel H.264 decoder on the cell broadband engine architecture
The H.264 video codec provides exceptional video compression while imposing dramatic increases in computational complexity over previous standards. While exploiting parallelism in...
Michael A. Baker, Pravin Dalale, Karam S. Chatha, ...