234 search results - page 47 / 47 » Architecture Implementation Using the Machine Description La... |
FDL
2003
IEEE
14 years 22 days ago
2003
IEEE
SystemC-Plus from the ODETTE project provides the ability to simulate and synthesise object-oriented specifications into hardware. The current ODETTE compiler translates each obj...
IFIP
2004
Springer
14 years 24 days ago
2004
Springer
The parallel packet switch (PPS) extends the inverse multiplexing architecture, and is extensively used as the core of contemporary commercial switches. A key factor in the perfor...
ICS
2007
Tsinghua U.
14 years 1 months ago
2007
Tsinghua U.
Software or hardware data cache prefetching is an efficient way to hide cache miss latency. However effectiveness of the issued prefetches have to be monitored in order to maximi...
WIESS
2000
13 years 8 months ago
2000
As IPC mechanisms become faster, stub-code efficiency becomes a performance issue for local client/server RPCs and inter-component communication. Inefficient and unnecessary compl...