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HPCA
1999
IEEE
13 years 11 months ago
Impulse: Building a Smarter Memory Controller
Impulse is a new memory system architecture that adds two important features to a traditional memory controller. First, Impulse supports application-specific optimizations through...
John B. Carter, Wilson C. Hsieh, Leigh Stoller, Ma...
SBACPAD
2006
IEEE
102views Hardware» more  SBACPAD 2006»
14 years 1 months ago
Ultra-Fast CPU Performance Prediction: Extending the Monte Carlo Approach
Performance evaluation of contemporary processors is becoming increasingly difficult due to the lack of proper frameworks. Traditionally, cycle-accurate simulators have been exte...
Ram Srinivasan, Jeanine Cook, Olaf M. Lubeck
NPC
2010
Springer
13 years 5 months ago
Exposing Tunable Parameters in Multi-threaded Numerical Code
Achieving high performance on today’s architectures requires careful orchestration of many optimization parameters. In particular, the presence of shared-caches on multicore arch...
Apan Qasem, Jichi Guo, Faizur Rahman, Qing Yi
WCRE
2002
IEEE
14 years 8 days ago
Estimating Potential Parallelism for Platform Retargeting
Scientific, symbolic, and multimedia applications present diverse computing workloads with different types of inherent parallelism. Tomorrow’s processors will employ varying com...
Linda M. Wills, Tarek M. Taha, Lewis B. Baumstark ...
IPPS
2005
IEEE
14 years 29 days ago
Technology-based Architectural Analysis of Operand Bypass Networks for Efficient Operand Transport
As semiconductor feature sizes decrease, interconnect delay is becoming a dominant component of processor cycle times. This creates a critical need to shift microarchitectural des...
Hongkyu Kim, D. Scott Wills, Linda M. Wills