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DAC
2005
ACM
13 years 11 months ago
Normalization at the arithmetic bit level
We propose a normalization technique for verifying arithmetic circuits in a bounded model checking environment. Our technique operates on the arithmetic bit level (ABL) descriptio...
Markus Wedler, Dominik Stoffel, Wolfgang Kunz
IPPS
2002
IEEE
14 years 2 months ago
System-Level Analysis for MPEG-4 Decoding on a Multi-Processor Architecture
The convergence of TV and new features such as Internet and games, requires a generic media-processing platform, that enables simultaneous execution of very diverse tasks, ranging...
Egbert G. T. Jaspers, Erik B. van der Tol, Peter H...
DAC
1994
ACM
14 years 1 months ago
Automatic Verification of Pipelined Microprocessors
Abstract - We address the problem of automatically verifying large digital designs at the logic level, against high-level specifications. In this paper, we present a methodology wh...
Vishal Bhagwati, Srinivas Devadas
VLSID
2007
IEEE
97views VLSI» more  VLSID 2007»
14 years 9 months ago
Efficient Microprocessor Verification using Antecedent Conditioned Slicing
We present a technique for automatic verification of pipelined microprocessors using model checking. Antecedent conditioned slicing is an efficient abstraction technique for hardw...
Shobha Vasudevan, Vinod Viswanath, Jacob A. Abraha...
TCSV
2008
129views more  TCSV 2008»
13 years 9 months ago
Efficient Architecture Design of Motion-Compensated Temporal Filtering/Motion Compensated Prediction Engine
Since motion-compensated temporal filtering (MCTF) becomes an important temporal prediction scheme in video coding algorithms, this paper presents an efficient temporal prediction ...
Yi-Hau Chen, Chih-Chi Cheng, Tzu-Der Chuang, Ching...