DAC 1994 - PDF Preprint Papers

DAC 1994 Design Automation Conference

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DAC
1994
ACM

196views Computer Architecture» more DAC 1994»

Probabilistic Analysis of Large Finite State Machines

14 years 4 months ago

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Regarding nite state machines as Markov chains facilitates the application of probabilistic methods to very large logic synthesis and formal verication problems. Recently, we ha...

Gary D. Hachtel, Enrico Macii, Abelardo Pardo, Fab...

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Id	Views	Title	Status

1	196	Probabilistic Analysis of Large Finite State Machines	claim
2	166	Boolean Matching Using Generalized Reed-Muller Forms	claim
3	157	Dynamic Search-Space Pruning Techniques in Path Sensitization	claim
4	152	Routing in a New 2-Dimensional FPGA/FPIC Routing Architecture	claim
5	149	The Design of High-Performance Microprocessors at Digital	claim
6	142	Statistical Delay Modeling in Logic Design and Synthesis	claim
7	134	Exact and Approximate Methods for Calculating Signal and Transition Probabilities in FSMs	claim
8	128	BDD Variable Ordering for Interacting Finite State Machines	claim
9	125	Loop Pipelining for Scheduling Multi-Dimensional Systems via Rotation	claim
10	124	Software Scheduling in the Co-Synthesis of Reactive Real-Time Systems	claim
11	121	Design Methodology Management Using Graph Grammars	claim
12	120	Stochastic Optimization Approach to Transistor Sizing for CMOS VLSI Circuits	claim
13	119	Rectilinear Steiner Trees with Minimum Elmore Delay	claim
14	118	Clock Period Optimization During Resource Sharing and Assignment	claim
15	118	A Global Router Optimizing Timing and Area for High-Speed Bipolar LSI's	claim
16	116	Minimal Delay Interconnect Design Using Alphabetic Trees	claim
17	115	A Communicating Petri Net Model for the Design of Concurrent Asynchronous Modules	claim
18	115	Optimum Functional Decomposition Using Encoding	claim
19	114	A Unified Approach to Multilayer Over-the-Cell Routing	claim
20	113	Calculation of Unate Cube Set Algebra Using Zero-Suppressed BDDs	claim
21	110	Acyclic Multi-Way Partitioning of Boolean Networks	claim
22	109	A Modular Partitioning Approach for Asynchronous Circuit Synthesis	claim
23	107	Experience with Image Compression Chip Design using Unified System Construction Tools	claim
24	106	Clock Grouping: A Low Cost DFT Methodology for Delay Testing	claim
25	106	Technology Mapping Using Fuzzy Logic	claim
26	106	Management Issues in Eda	claim
27	106	Statistical Estimation of the Switching Activity in Digital Circuits	claim
28	104	ASTRX/OBLX: Tools for Rapid Synthesis of High-Performance Analog Circuits	claim
29	104	Incorporating Speculative Execution in Exact Control-Dependent Scheduling	claim
30	104	New Techniques for Efficient Verification with Implicitly Conjoined BDDs	claim
31	103	Simultaneous Placement and Module Optimization of Analog IC's	claim
32	103	An Efficient Approach to Transmission Line Simulation Using Measured or Tabulated S-parameter Data	claim
33	102	Memory Estimation for High Level Synthesis	claim
34	101	A Fully Implicit Algorithm for Exact State Minimization	claim
35	100	Automated Multi-Cycle Symbolic Timing Verification of Microprocessor-Based Designs	claim
36	100	Placement and Routing for a Field Programmable Multi-Chip Module	claim
37	99	Automatic Verification of Pipelined Microprocessors	claim
38	99	Exact Minimum Cycle Times for Finite State Machines	claim
39	99	Data Flow Partitioning for Clock Period and Latency Minimization	claim
40	98	OTTER: Optimal Termination of Transmission Lines Excluding Radiation	claim
41	96	Permissible Observability Relations in FSM Networks	claim
42	95	Performance-Driven Simultaneous Place and Route for Row-Based FPGAs	claim
43	94	Delay Analysis of VLSI Interconnections Using the Diffusion Equation Model	claim
44	93	Chain Closure: A Problem in Molecular CAD	claim
45	93	An Efficient Path Delay Fault Coverage Estimator	claim
46	93	Fitting Formal Methods into the Design Cycle	claim
47	92	Layout Driven Logic Synthesis for FPGAs	claim
48	92	Optimizing Resource Utilization and Testability Using Hot Potato Techniques	claim
49	91	Cost of Silicon Viewed from VLSI Design Perspective	claim
50	89	Synthesis of Instruction Sets for Pipelined Microprocessors	claim
51	88	Error Diagnosis for Transistor-Level Verification	claim
52	86	Partitioning Very Large Circuits Using Analytical Placement Techniques	claim
53	85	Performance Analysis and Optimization of Schedules for Conditional and Loop-Intensive Specifications	claim
54	81	RC Interconnect Optimization Under the Elmore Delay Model	claim
55	79	HSIS: A BDD-Based Environment for Formal Verification	claim
56	79	MIST - A Design Aid for Programmable Pipelined Processors	claim
57	74	Functional Test Generation for FSMs by Fault Extraction	claim

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