218 search results - page 25 / 44 » Architecture Level Power-Performance Tradeoffs for Pipelined... |
CGF
2010
13 years 9 months ago
2010
We propose a new framework design for exploiting multi-core architectures in the context of visualization dataflow systems. Recent hardware advancements have greatly increased the...
EH
2004
IEEE
14 years 22 days ago
2004
IEEE
The use of Application Specific Instruction-set Processors (ASIP) in embedded systems is a solution to the problem of increasing complexity in the functions these systems have to ...
ECBS
2003
IEEE
14 years 2 months ago
2003
IEEE
Polymorphous computer-based systems are systems in which the CPU architecture “morphs” or changes shape to meet the requirements of the application. Optimized and efficient de...
DAC
2002
ACM
14 years 10 months ago
2002
ACM
The design of high-throughput large-state Viterbi decoders relies on the use of multiple arithmetic units. The global communication channels among these parallel processors often ...
SBCCI
2005
ACM
14 years 2 months ago
2005
ACM
Flow control mechanisms in Network-on-Chip (NoC) architectures are critical for fast packet propagation across the network and for low idling of network resources. Buffer manageme...