1381 search results - page 110 / 277 » Architecture and Design of a High Performance SRAM for SOC D... |
DAC
2011
ACM
12 years 8 months ago
2011
ACM
A three-dimensional (3D) CMOS imager constructed from stacking a pixel array of image sensors, an analog-to-digital converter (ADC) array, and an image signal processor (ISP) arra...
DEBU
2006
13 years 8 months ago
2006
Performance tuning in modern database systems requires a lot of expertise, is very time consuming and often misdirected. Tuning attempts often lack a methodology that has a holist...
ERSA
2004
13 years 9 months ago
2004
In this paper, we propose an architecture for floatingpoint based LU decomposition for large-sized matrices. Our proposed architecture is based on the well known concept of blocki...
COMCOM
2006
13 years 8 months ago
2006
There exists a high demand for reliable, high capacity underwater acoustic networks to allow efficient data gathering and information exchange. This is evidenced by significant re...
LCN
2008
IEEE
14 years 2 months ago
2008
IEEE
— IP traffic measurements form the basis of several network management tasks, such as accounting, planning, intrusion detection, and charging. High-speed network links challenge ...