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SBACPAD
2007
IEEE
130views Hardware» more  SBACPAD 2007»
14 years 2 months ago
Design of a Feasible On-Chip Interconnection Network for a Chip Multiprocessor (CMP)
In this paper, an adaptive wormhole router for a flexible on-chip interconnection network is proposed and implemented for a Chip-Multi Processor (CMP). It adopts a wormhole switc...
Seung Eun Lee, Jun Ho Bahn, Nader Bagherzadeh
IPPS
2007
IEEE
14 years 2 months ago
A Study of Design Efficiency with a High-Level Language for FPGAs
Over the years reconfigurable computing devices such as FPGAs have evolved from gate-level glue logic to complex reprogrammable processing architectures. However, the tools used f...
Zain-ul-Abdin, Bertil Svensson
ISLPED
2005
ACM
103views Hardware» more  ISLPED 2005»
14 years 1 months ago
A technique for low energy mapping and routing in network-on-chip architectures
Network-on-chip (NoC) has been proposed as a solution for the global communication challenges of System-on-chip (SoC) design in the nanoscale technologies. NoC design with mesh ba...
Krishnan Srinivasan, Karam S. Chatha
SECON
2008
IEEE
14 years 2 months ago
A Multi-AP Architecture for High-Density WLANs: Protocol Design and Experimental Evaluation
—Fast proliferation of IEEE 802.11 wireless devices has led to the emergence of High-Density (HD) Wireless Local Area Networks (WLANs), where it is challenging to improve the thr...
Yanfeng Zhu, Zhisheng Niu, Qian Zhang, Bo Tan, Zhi...
ISPASS
2007
IEEE
14 years 2 months ago
CA-RAM: A High-Performance Memory Substrate for Search-Intensive Applications
This paper proposes a specialized memory structure called CA-RAM (Content Addressable Random Access Memory) to accelerate search operations present in many important real-world ap...
Sangyeun Cho, Joel R. Martin, Ruibin Xu, Mohammad ...