1381 search results - page 72 / 277 » Architecture and Design of a High Performance SRAM for SOC D... |
ANCS
2005
ACM
14 years 1 months ago
2005
ACM
Hash tables provide efficient table implementations, achieving O(1), query, insert and delete operations at low loads. However, at moderate or high loads collisions are quite freq...
ET
2002
13 years 8 months ago
2002
As System on a Chip (SoC) testing faces new challenges, some new test architectures must be developed. This paper describes a Test Access Mechanism (TAM) named CASBUS that solves ...
FPL
2006
Springer
13 years 11 months ago
2006
Springer
A field-programmable gate array (FPGA) implementation of a new detection algorithm for uncoded multiple inputmultiple output (MIMO) systems based on the complex version of the sph...
ISCA
2009
IEEE
14 years 2 months ago
2009
IEEE
The memory subsystem accounts for a significant cost and power budget of a computer system. Current DRAM-based main memory systems are starting to hit the power and cost limit. A...
ICCD
2004
IEEE
14 years 5 months ago
2004
IEEE
Networks-on-Chip (NoC), a new SoC paradigm, has been proposed as a solution to mitigate complex on-chip interconnect problems. NoC architecture consists of a collection of IP core...