In this paper we introduce Resizable Data Composer-Cache (RDC-Cache). This novel cache architecture operates correctly at sub 500 mV in 65 nm technology tolerating large number of...
Avesta Sasan, Houman Homayoun, Ahmed M. Eltawil, F...
This paper will discuss high performance clustering from a series of critical topics: architectural design, system software infrastructure, and programming environment. This will ...
David A. Bader, Arthur B. Maccabe, Jason R. Mastal...
In this work, we propose and investigate the idea of enhancing a System-on-Chip (SoC) communication architecture (the fabric that integrates system components and carries the comm...
Joel Coburn, Srivaths Ravi, Anand Raghunathan, Sri...
The Common Component Architecture (CCA) defines a specification for the implementation of frameworks to support component-based high performance applications. The same framework s...
Madhusudhan Govindaraju, Himanshu Bari, Michael J....
As multiprocessor systems-on-chip become a reality, performance modeling becomes a challenge. To quickly evaluate many architectures, some type of high-level simulation is require...
Joshua J. Pieper, Alain Mellan, JoAnn M. Paul, Don...