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CASES
2009
ACM
13 years 11 months ago
A fault tolerant cache architecture for sub 500mV operation: resizable data composer cache (RDC-cache)
In this paper we introduce Resizable Data Composer-Cache (RDC-Cache). This novel cache architecture operates correctly at sub 500 mV in 65 nm technology tolerating large number of...
Avesta Sasan, Houman Homayoun, Ahmed M. Eltawil, F...
IWCC
1999
IEEE
14 years 13 days ago
Design and Analysis of the Alliance/University of New Mexico Roadrunner Linux SMP SuperCluster
This paper will discuss high performance clustering from a series of critical topics: architectural design, system software infrastructure, and programming environment. This will ...
David A. Bader, Arthur B. Maccabe, Jason R. Mastal...
CASES
2005
ACM
13 years 10 months ago
SECA: security-enhanced communication architecture
In this work, we propose and investigate the idea of enhancing a System-on-Chip (SoC) communication architecture (the fabric that integrates system components and carries the comm...
Joel Coburn, Srivaths Ravi, Anand Raghunathan, Sri...
CIC
2004
114views Communications» more  CIC 2004»
13 years 9 months ago
Design of Distributed Component Frameworks for Computational Grids
The Common Component Architecture (CCA) defines a specification for the implementation of frameworks to support component-based high performance applications. The same framework s...
Madhusudhan Govindaraju, Himanshu Bari, Michael J....
DAC
2004
ACM
14 years 9 months ago
High level cache simulation for heterogeneous multiprocessors
As multiprocessor systems-on-chip become a reality, performance modeling becomes a challenge. To quickly evaluate many architectures, some type of high-level simulation is require...
Joshua J. Pieper, Alain Mellan, JoAnn M. Paul, Don...